In this paper a new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area und the power dissipation only the sum bits of the udder cells are duplicated. This is possible since the input parity is determined by use of internal nodes of the udder cells. The adder is modeled by a SYNOPSIS CAD tool from the EUROCHIPProjec t with a standard library. With respect to duplication and comparison the necessary urea and the power dissipation can be reduced up to 38 9% and up to 29 % respectively compared to an increase of the maximal delay of only 12 %.
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